1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
2. Description of the Related Art
A semiconductor memory device, in general, is classified as either volatile or non-volatile. Volatile semiconductor memory devices, such as dynamic random access memory (DRAM) devices and/or static random access memory (SRAM) devices, have a relatively high response speed. However, the volatile semiconductor memory devices lose data stored therein when power is shut off. Although non-volatile semiconductor memory devices, such as electrically erasable programmable read only memory (EEPROM) devices and/or flash memory devices, have a relatively slow response speed, non-volatile semiconductor memory devices can maintain data stored therein when power is shut off. In EEPROM devices, data is electrically stored (i.e., programmed) or erased through a Fowler-Nordheim (F-N) tunneling mechanism and/or a channel hot electron injection mechanism.
For example, U.S. Pat. No. 6,465,293 discloses a method of manufacturing a flash memory cell. In accordance with the disclosure in U.S. Pat. No. 6,465,293, a method of manufacturing a flash memory cell includes the steps of forming an oxide layer on a semiconductor substrate in which a device isolation layer is formed, patterning the oxide layer to expose the semiconductor substrate at a portion in which a floating gate will be formed to thereby form an oxide layer pattern, sequentially forming a tunnel insulating layer and a first polysilicon layer on the entire structure, planarizing the first polysilicon layer until the oxide layer pattern is exposed to thereby form a floating gate, etching the tunnel insulating layer and the oxide layer pattern in the exposed portion to a given thickness, forming a dielectric layer on the entire structure, sequentially forming a second polysilicon layer, a tungsten suicide layer and a hard mask, patterning the second polysilicon layer, the tungsten silicide layer and the hard mask to form a control gate, and injecting impurity ions into the semiconductor substrate at the both sides of the floating gate to form a junction region.
The floating gate is self-aligned by the oxide layer pattern partially exposing the semiconductor substrate.
As a packing density of the semiconductor device has become more highly integrated, an aspect ratio of an opening defined by the oxide layer pattern (by which a portion of the semiconductor substrate is exposed) has been increased, thereby generating void(s) in the first polysilicon layer filling up the opening.
The void(s) generated in the first polysilicon layer is opened during the planarization process of the first polysilicon layer, and thus an opened seam is formed at a surface of the floating gate. The opened seam deteriorates a breakdown voltage characteristic of the dielectric film formed on the floating gate and a coupling ratio of the flash memory device. Further, leakage current characteristic through the dielectric film is deteriorated.
In the case of partially removing the first polysilicon layer to remove the void(s) in the first polysilicon layer and then forming an additional polysilicon layer on the first polysilicon layer, the tunnel insulating layer between the first polysilicon layer and the semiconductor substrate is damaged by the etchant used during the etching process for removing the void(s). As a result, breakdown voltage characteristic of the tunnel insulating layer is deteriorated.